Now Hiring - Verification Applications Engineer in Mountain View, CA

Inclusively is partnering with a electronic design automation to hire a Verification Applications Engineer.

ABOUT INCLUSIVELY:

Inclusively is a digital tech platform that connects candidates with disabilities, who may benefit from workplace accommodations, to inclusive employers. This includes all disabilities under the ADA, including mental health conditions (e.g. anxiety, depression, PTSD), chronic illnesses (e.g. diabetes, Long COVID), and neurodivergence (e.g. autism, ADHD). Applicants with one or more of these conditions are encouraged to apply; Inclusively does not require applicants to disclose their specific disability.

We are looking for an Applications Engineer to join the team.

Does this sound like a good role for you?

The primary focus of this role is to support the sale and adoption of the Company Verification solution. The candidate will be part of a fast-paced Applications Engineering team, providing technical support and driving the effort to enable the methodology and solutions in the verification domain with emphasis on simulation and low power. The Engineer is expected to possess in-depth knowledge of RTL simulation and System Verilog/UVM testbench development with solid debugging skills. The candidate should have hands-on experience with UVM, as well as Assertion and Randomized Constraints based verification methodologies. Knowledge and prior experience working on low power simulation is a plus. In this role, the AE will work directly with customers to assist with the deployment of the verification tools and methodologies, resolve technical issues and provide technical training. The responsibilities include product demonstrations, evaluations, and post-sales support.

Key Qualifications:

• BS in CS/EE with 6+ years of experience, MS in CS/EE preferred.
• Solid knowledge of System Verilog/UVM, Verilog is required; VHDL preferred.
• Minimum 5 years of experience with Block Level and SOC Level simulation verification is required.
• Knowledge of Constrained Random Verification and Code/Functional/Assertions (SVA) Coverage closure.
• Experienced debugging skills on designs and System Verilog/UVM environment is needed, with debugging tools such as Verdi.
• Critical thinking and problem solving skills.
• Good verbal and written presentation/communication skills and excellent organization skills.
• Good customer interface skills.

Preferred Experience:

• Knowledge of low power simulation with UPF.

The base salary range across the U.S. for this role is between $106,000-$185,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. The Company offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Job Type: Full-time

Pay: $106,000.00 - $185,000.00 per year

Schedule:

• Monday to Friday
• Weekends as needed

Work Location: In person